Physical Design Engineer will be responsible for all aspects of physical implementation from RTL to GDS, including RTL synthesis, scan stitching, timing constraints creation, Power analysis, chip floor plan, clock distribution, full chip assembly, Timing driven Placement & Route, Static Timing Analysis, timing closure, ECO and Tape-out.
The Physical Design Engineer will Interface with other design groups to ensure time to market and quality of results. Will participate in design/architecture reviews, establishing & defining physical design methodologies and flow automation. The key to this job is STA or static timing analysis; experience with Primetime a plus
The Physical Design Engineer Job Requirements:
- 5+ years of experience in a Logic design or Physical Design position
- Minimum Education – Bachelor’s Degree BSEE or MSEE is ideal
- Worked on/written timing constraints
- Experience with clock tree synthesis
- Strong knowledge of RTL design
- Familiar with RTL compiler/Design Compiler, ICC/SOC Encounter
- Primetime experience is ideal
- Scan insertion, ATPG and DFT
- RTL logic knowledge and some experience
- Excellent communictation skills and able to work in a fast-pace team environment
Apply Directly Now
Industry: Physical Design Engineer, Semiconductor, RTL design, Scan insertion, ATPG, DFT, Primetime
Phone: +1 919-521-5253
